As the high integration of semiconductor devices has been progressed, a field effect transistor (MISFET: Metal Insulator Semiconductor Field Effect Transistor) has been miniaturized according to the scaling law. However, a problem rises that the resistances of the gate and source/drain are increased, and high-speed operations cannot be provided even if the field effect transistor is miniaturized. Accordingly, studies have been made on a salicide technology by which a low resistant metal silicide layer, for example, a nickel silicide layer or cobalt silicide layer is formed by self-alignment on a surface of a conductive film forming a gate and a surface of a semiconductor region forming a source/drain, thereby lowering the resistances of the gate and source/drain.
In Japanese Patent Application Laid-Open Publication No. 2005-109504 (Patent Document 1), there is described a technology about a method of manufacturing a semiconductor element including: a stage of forming a metal layer on a gate electrode and a source/drain region; a stage of treating a surface of the metal layer by use of Ar plasma; and a stage of annealing a silicon substrate on which the metal layer is formed at a predetermined temperature to form a thin silicide film.
In Japanese Patent Application Laid-Open Publication No. 2006-294861 (Patent Document 2), there is described a technology about a method of depositing a metal-contained film on a surface of Si-contained portion, the method comprises: a physical surface treatment step of physically processing the surface of the Si-contained portion by means of plasma using a high frequency; a chemical surface treatment step of chemically processing the surface of the plasma-treated Si-contained portion by reactive gas; and a film forming step of forming a metal-contained film on the Si-contained portion after the chemical surface treatment.
In Japanese Patent Application Laid-Open Publication No. 2003-119564 (Patent Document 3), there is described a technology where, after a natural oxide film on a surface of a Si substrate is removed in a chamber of a plasma CVD apparatus, a film containing a high-melting-point metal is deposited on the Si substrate from which the natural oxide film has been removed in series without exposing the Si substrate from which the natural oxide film has been removed to air in the same chamber in which etching and deposition are optimized.
In Japanese Patent Application Laid-Open Publication No. H07-38104 (Patent Document 4), there is described a technology where a Ni film and a metal compound film are deposited sequentially on the entire surface of an Si substrate on which a diffusion layer to become a source/drain is formed, and a nickel silicide is then formed on the surface of the diffusion layer to become the source/drain by reacting Ni and Si by heat treatment, and the unreacted Ni and the metal compound film are removed, thereby stably depositing the nickel silicide film without forming insulating matter in the nickel silicide.